Digital Phase-locked loop (DPLL) circuits are frequently utilized to lock an oscillator in phase with an applied reference signal. DPLL circuits are often utilized within receivers in digital communication systems, for example, to generate a local clock signal that is phase aligned with an incoming reference signal. The phase aligned local clock signal facilitates the receipt and processing of data sent by a transmitter in the communication system.
A conventional DPLL circuit includes a phase detector, a filter and a digital controlled oscillator (DCO). In the conventional DPLL circuit, the phase detector compares the incoming reference signal and the output of the DCO. The phase detector generates an error signal that is representative of the phase difference of the reference signal and the DCO output. The error signal is filtered and applied to the control input of the DCO to produce an output signal that tracks the phase of the reference signal.
FIG. 1 is a block diagram of an exemplary conventional DPLL circuit 100. As shown in FIG. 1, the DPLL circuit 100 comprises a phase detector 110, a digital filter 120, a digital controlled oscillator 130 and a divider 140. Generally, the phase detector 110 compares the frequency of the two input signals (an applied reference clock, RCK, and a feedback clock, FCK) and generates one or more error signals, such as UP and DOWN (DN), that provide a measure of the phase difference between the two input signals. As shown in FIG. 1, the exemplary error signals, UP and DOWN, are applied to the digital filter 120 which generates a binary error value, such as an 8 bit error value in the exemplary embodiment. The binary error value is applied to the digital controlled oscillator 130 and causes the digital controlled oscillator 130 to deviate in the direction of the reference signal, RCK. Eventually, the digital controlled oscillator 130 will “lock” and maintain a fixed relationship with the reference signal, RCK. It is noted that an additional divider (not shown) may be positioned between the input of the reference signal, RCK, and the phase detector 110.
There are a number of known implementations for the phase detector 110 of FIG. 1. FIG. 2 is a circuit diagram of an exemplary conventional phase detector 110 of FIG. 1. As shown in FIG. 2, the exemplary phase detector 110 is comprised of two flip-flops, FF1 and FF2, and a NAND gate 220. The UP and DN pulses, which occur on the basis of phase differences between the two clocks FCK and RCK, are updated on the positive edges of the two clocks, FCK and RCK, in a known manner. Each flip-flop, FF1 and FF2, samples a corresponding applied input clock signal and the NAND gate 220 performs a comparison operation that indicates which applied clock is leading. Generally, the UP signal indicates that the output of the digital controlled oscillator 130 is too slow, relative to the applied reference clock, while the DOWN signal indicates that the output of the digital controlled oscillator 130 is too fast, relative to the applied reference clock. The output of the NAND gate 220 is applied as a reset to each flip-flop, FF1 and FF2. The output of the NAND gate 220 has a binary value of logic one, whenever one or both flip-flops are low. The output of the NAND gate 220 has a binary value of logic zero whenever both flip-flops are high. Thus, when the two applied clocks are aligned, the flip-flop outputs will both have values of logic zeros.
A number of techniques have been proposed or suggested for improving the frequency locking characteristics of such PLL circuits. For example, one technique has proposed reducing the duration of the reset pulse to shorten the unused time between each update period. This proposal, however, requires the use of additional capacitors, delay elements and logic differential amplifiers that are not shown in FIG. 2. It has been found, however, that under certain conditions, the flip-flops, FF1 and FF2, would not reset properly and the PLL circuit 100 will eventually lock onto the wrong frequency when the reset pulse is not long enough.
A need therefore exists for methods and apparatus for digital phase detection with improved frequency locking characteristics.